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Overview: 

➢16 bit Analog-Front-End (AFE) for digitizing analog outputs from CIS sensors.

➢ Both LVDS interface version and parallel interface are available.

Features:

➢ 16-bit ADC

➢ 60MSPS Conversion Rate, 20MSPS/Channel

➢ Single, 2 or 3 Channel Operation

➢ Optical Sensor Signal Processing Sample-Hold for CIS Sensor

➢ 9-bit Programmable Gain (0.5x – 8.0x)

➢ 10-bit Offset Control (± 300mV)

➢ 7-bit Reference Voltage (0.8V – 1.3V)

➢ 3 channel-LED Driver (3-66mA/CH) and Timing Generator for LED Driver

➢ Parallel or LVDS Interface

➢ LVDS-Clock-Input-Receiver and Single-Clock- Input Circuit.

➢ Build in Timing Generator for CIS driving.

➢ Build in Sync Generator for generating Horizontal Sync-Signal (SI), and 3 Channels of General Purpose IO.

➢ 75dB Input Referred SNR with 0dB-Analog-Gain

➢ Build in 4 Channels of LDO for 2V-Power-Supply

Detailed information: 

Please click here to contact Art Analog for further information!

Block Diagram of LVDS version	Block Diagram of parallel version